The present invention relates to a time delay circuit and method and more particularly to a circuit for creating a controllable time delay used in phase shifting a digital signal.
Data phase alignment circuitry, digital phase locked loops (PLL) and other digital circuits utilize variable time delay circuitry to achieve digital signal phase alignment, phase offset or sampling timing. One approach used for variable time delay is digital variable time delay circuitry that contains a programmable counter. The resolution of such circuits is generally limited by the clock speed. Increasing the frequency of the clock increases resolution, but the clock frequency is limited by the speed of the digital circuits. Also, the high frequency clock generally increases power consumption.
Another approach used for variable time delay utilizes an analog PLL with a ring oscillator containing M stages. Such an approach is illustrated in FIG. 1. Referring to FIG. 1, the analog PLL 10 locks to the reference signal 11 or data rate signal. The analog PLL 10 maintains the frequency as N* the data rate and generates M*N phases from the outputs of ring oscillator 12. Thus, the resolution is M*N using N* the data rate clock frequency. Increasing the number of stages M, increases the resolution since the resolution of this approach is limited by stage number M and the speed of phase selector 13. Typically, the delay of each path of phase selector 13 must be the same and increasing M makes the path matching difficult. When using the analog PLL approach, phase selector 13 can make narrow pulses when making large phase changes. Because the phase selector 13 and a divider 14 condition these pulses, the phase selector 13 and the divider 14 must work at much higher frequency than the N* data rate frequency. The speed limits of the phase selector 13 and divider 14 thus limit the resolution in this typical digital variable phase shift circuitry approach.
Thus, previous techniques have resolution limited by digital element speed and it would be desirable to have a variable time delay that achieves high resolution beyond the speed limitations described above.